In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
A current drive in the semiconductor device industry is to produce semiconductors having an increasingly large density of integrated circuits which are ever-decreasing in size. These goals are achieved by scaling down the size of the circuit features in both the lateral and vertical dimensions. Vertical downscaling requires that the thickness of gate oxides on the wafer be reduced by a degree which corresponds to shrinkage of the circuit features in the lateral dimension. While there are still circumstances in which thicker gate dielectrics on a wafer are useful, such as to maintain operating voltage compatibility between the device circuits manufactured on a wafer and the current packaged integrated circuits which operate at a standard voltage, ultrathin gate dielectrics will become increasingly essential for the fabrication of semiconductor integrated circuits in the burgeoning small/fast device technology.
The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects, or the layers of separate electrical conductors which are formed on top of a substrate and connect various functional components of the substrate and other electrical connections to the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by via interconnects, which are post- or plug-like vertical connections between the conductors of the interconnect layers and the substrate. ICs often have five or more interconnect layers formed on top of the substrate.
Only a relatively short time ago, it was impossible or very difficult to construct an IC with more than one or two layers of interconnects. The topology variations created by forming multiple layers on top of one another resulted in such significant depth of focus problems with lithographic processes that any further additions of layers were neardly impossible to achieve. However, recent advances in semiconductor fabrication planarization techniques, such as chemical mechanical polishing (CMP), have been successful in smoothing relatively significant variations in the height or topography of each interconnect layer. As a result of the smoothing, or planarization, conventional lithographic processes are repetitively used without significant limitation to form considerably more layers of interconnects than had previously been possible.
The multiple interconnect layers occupy volume within the IC, although they do not necessarily occupy additional substrate surface area. Nevertheless, because surface area and volume are critical considerations in Ics, attention has been focused on the effective use of the space between the interconnect layers. Normally, the space between the interconnect layers is occupied by an insulating material, known as an interlayer dielectric (ILD) or intermetal dielectric (IMD), to insulate the electrical signals conducted by the various conductors of the interconnect layers from each other and from the functional components in the underlying substrate.
One effective use for the space between the interconnect layers is the incorporation of capacitors between the interconnect layers in the IMD insulating material separating the interconnect layers. These capacitors form part of the functional components of the IC. Previously, capacitors were constructed in the first layers of IC fabrication immediately above the substrate alongside other structures, such as transistors, so the capacitors were formed of generally the same material used to construct the other functional components, such as polysilicon. Capacitors formed of these materials are generally known as poly-plate capacitors.
Because the conductors of the interconnect layers are metal in construction, the capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction to take advantage of processing steps and performance enhancements. A MIM capacitor has metal plates which are usually formed on the metal conductors of the interconnect layers. Because metal fabrication is required for the conductors of the interconnect layers, the simultaneous or near-simultaneous formation of the metal capacitor plates is readily accomplished without significant additional process steps and manufacturing costs.
MIM capacitors are very valuable in many applications of semiconductor technology. For example, MIMs can be used in RF circuits, analog ICs, high power microprocessor units (MPUs), and DRAM cells. However, alignment marks which lie at the junction of the substrate and the base dielectric layer deposited on the substrate and are important for semiconductor processing, are obscured by the opaque metal layers and transparent IMD layers that are sequentially deposited on the base dielectric layer and on each other. Thus, during fabrication of MIM capacitors it frequently becomes necessary to cut through the metal layers and the intervening dielectric layer or layers of the MIM capacitor to the transparent base dielectric layer on the substrate in order to expose the alignment marks through the layer.
A sectional view of an MIM capacitor 200, with associated structures, fabricated on a wafer substrate 100 is shown in FIG. 1. Preparatory to fabrication of the MIM capacitor 200, metal lines 120, 121 are deposited on the substrate 100. A base dielectric layer 110 is next deposited on the substrate 100 and the metal lines 120, 121.
A bottom metal layer 160, an intermetal dielectric (IMD) layer 170 and an upper metal layer 180 are sequentially deposited above the base dielectric layer 110. An upper dielectric layer 210 is deposited on the base dielectric layer 110 and the upper metal layer 180 of the capacitor 200. Metal lines 250, 251 are fabricated on the upper dielectric layer 210.
A conductive via 150 extends through the base dielectric layer 110 and establishes electrical communication between the metal line 121 and bottom metal layer 160 of the capacitor 200. A conductive via 230 extends through the upper dielectric layer 210 and establishes electrical communication between the metal line 250 and the upper metal layer 180 of the capacitor 200. A conductive via 240 extends through the upper dielectric layer 210 and the base dielectric layer 110 and establishes electrical communication between the metal lines 120 and 251.
Typically, each of the bottom metal layer 160 and the top metal layer 180 is a thin (<2 kA) film of AlCu, and may further include a deposit of TiN or TaN. To enhance electromagnetic properties of the capacitor 200, the bottom metal layer 160 is deposited on the base dielectric layer 110 and the top metal layer 180 is deposited on the IMD layer 170 using a physical vapor deposition (PVD) metal sputtering technique which is carried out at a relatively high temperature (typically about >270 degrees C.). However, at such high deposition temperatures, difficulty is encountered in controlling the thickness uniformity of the layers 160, 180. Furthermore, the high deposition temperatures cause excessive AlCu grain agglomeration in the layers and excessive surface roughness to the upper surface of the layers. Accordingly, a new and improved low-temperature metal deposition method is needed for the deposition of metal layers, particularly AlCu layers in the fabrication of MIM capacitors, for example.
An object of the present invention is to provide a novel method which is suitable for depositing a metal on a substrate.
Another object of the present invention is to provide a novel method which is suitable for depositing a metal of substantially uniform thickness on a substrate.
Still another object of the present invention is to provide a novel method which is suitable for reducing grain agglomeration in a metal layer during layer deposition.
Yet another object of the present invention is to provide a novel method which is suitable for depositing thin metal films in the fabrication of MIM (metal-insulator-metal) capacitors.
A still further object of the present invention is to provide a novel low temperature metal deposition method which includes depositing a metal film on a substrate at reduced temperatures to enhance the thickness uniformity of the metal film and reduce grain agglomeration in the film.
Another object of the present invention is to provide a novel low temperature metal deposition method characterized by intrinsic breakdown voltage improvement.